Graphics

Catlab.Graphics.Graphviz.to_graphvizMethod

Draw an undirected wiring diagram using Graphviz.

Creates an undirected, bipartite Graphviz graph, with the boxes and outer ports of the diagram becoming nodes of one kind and the junctions of the diagram becoming nodes of the second kind.

Arguments

  • graph_name="G": name of Graphviz graph
  • prog="neato": Graphviz program, usually "neato" or "fdp"
  • box_labels=nothing: name of diagram data for box label
  • port_labels=true: label ports with their number
  • junction_labels=nothing: name of diagram data for junction label
  • junction_size="0.075": size of junction nodes, in inches
  • implicit_junctions=false: whether to represent a junction implicity as a wire when it has exactly two incident ports
  • graph_attrs=Dict(): top-level graph attributes
  • node_attrs=Dict(): top-level node attributes
  • edge_attrs=Dict(): top-level edge attributes
Catlab.Graphics.Graphviz.to_graphvizMethod

Draw a wiring diagram using Graphviz.

The input f can also be a morphism expression, which is converted into a wiring diagram.

Arguments

  • graph_name="G": name of Graphviz digraph
  • orientation=TopToBottom: orientation of layout. One of LeftToRight, RightToLeft, TopToBottom, or BottomToTop.
  • node_labels=true: whether to label the nodes
  • labels=false: whether to label the edges
  • label_attr=:label: what kind of edge label to use (if labels is true). One of :label, :xlabel, :headlabel, or :taillabel.
  • port_size="24": minimum size of ports on box, in points
  • junction_size="0.05": size of junction nodes, in inches
  • outer_ports=true: whether to display the outer box's input and output ports. If disabled, no incoming or outgoing wires will be shown either!
  • anchor_outer_ports=true: whether to enforce ordering of the outer box's input and output, i.e., ordering of the incoming and outgoing wires
  • graph_attrs=Dict(): top-level graph attributes
  • node_attrs=Dict(): top-level node attributes
  • edge_attrs=Dict(): top-level edge attributes
  • cell_attrs=Dict(): main cell attributes in node HTML-like label
Catlab.Graphics.GraphvizWiringDiagrams.graphviz_layoutMethod

Lay out directed wiring diagram using Graphviz.

Note: At this time, only the positions and sizes of the boxes, and the positions of the outer ports, are used. The positions of the box ports and the splines for the wires are ignored.

Catlab.Graphics.WiringDiagramLayoutsModule

Backend-agnostic layout of wiring diagrams via morphism expressions.

This module lays out wiring diagrams for visualization, independent of any specific graphics system. It uses the structure of a morphism expression to determine the layout. Thus, the first step of the algorithm is to convert the wiring diagram to a symbolic expression, using the submodule WiringDiagrams.Expressions. Morphism expressions may also be given directly.

Catlab.Graphics.WiringDiagramLayouts.layout_diagramMethod

Lay out a wiring diagram or morphism expression for visualization.

If a wiring diagram is given, it is first to converted to a morphism expression.

The layout is calculated with respect to a cartesian coordinate system with origin at the center of the diagram and the positive y-axis pointing downwards. Box positions are relative to their centers. All positions and sizes are dimensionless (unitless).

Catlab.Graphics.YFilesWiringDiagramsModule

Deserialize abstract wiring diagram from yFiles.

Reads a wiring diagram from the GraphML dialect used by yEd and yFiles. Unlike the GraphML spec, the yEd data model does not explicitly include ports:

  • https://yed.yworks.com/support/qa/102/
  • https://yed.yworks.com/support/qa/2531/

We infer the ports of boxes and their order from the geometry of the diagram. Thus, this module has the nature of a hack. While it may be useful for interactive and exploratory work, it should not be used in a production system.