Wiring diagrams

Generic data structures for wiring diagrams (aka, string diagrams).

A (directed) wiring diagram consists of a collection of boxes with input and output ports connected by wires. A box can be atomic (possessing no internal structure) or can itself be a wiring diagram. Thus, wiring diagrams can be nested recursively. Wiring diagrams are closely related to what the CS literature calls "directed graphs with ports" or more simply "port graphs". The main difference is that a wiring diagram has an "outer box": a wiring diagram has its own ports that can be connected to the ports of its boxes.

This module provides a generic data structure for wiring diagrams. Arbitrary data can be attached to the boxes, ports, and wires of a wiring diagram. The diagrams are "abstract" in the sense that they cannot be directly rendered as raster or vector graphics. However, they form a useful intermediate representation that can be serialized to and from GraphML or translated into Graphviz or other declarative diagram languages.

Base type for any box (node) in a wiring diagram.

This type represents an arbitrary black box with inputs and outputs.

An atomic box in a wiring diagram.

These boxes have no internal structure.

A port on a box to which wires can be connected.

Kind of port: input or output.

A wire connecting one port to another.

A directed wiring diagram, aka a string diagram.

The wiring diagram is implemented using the following internal data structures. A LightGraphs DiGraph stores the "skeleton" of the diagram: a simple directed graph with the boxes as vertices and with an edge between two vertices iff there is at least one wire between the corresponding boxes. There are two special vertices, accessible via input_id and output_id, representing the input and output ports, respectively.

The DiGraph is wrapped inside a MetaDiGraph to attach properties to the vertices and edges. For each edge, an edge property stores the list of wires between the source and target boxes.

Encapsulate multiple boxes within a single sub-diagram.

This operation is a (one-sided) inverse to subsitution (see substitute).

Create an encapsulating box for a set of boxes in a wiring diagram.

To a first approximation, the union of input ports of the given boxes will become the inputs ports of the encapsulating box and likewise for the output ports. However, when copies or merges occur, as in a cartesian or cocartesian category, a simplification procedure may reduce the number of ports on the encapsulating box.

Specifically:

1. Each input port of an encapsulated box will have at most one incoming wire

from the encapsulating outer box, and each output port of an encapsulated box will have at most one outgoing wire to the encapsulating outer box.

1. A set of ports connected to the same outside (non-encapsulated) ports will be

simplified into a single port of the encapsulating box.

See also induced_subdiagram.

Retrieve the underlying LightGraphs graph.

Do not mutate it! All mutations should pass through the WiringDiagram methods: add_box!, rem_box!, etc.

Get all wires coming into the port.

Get all wires coming into the box.

The wiring diagram induced by a subset of its boxes.

See also encapsulated_subdiagram.

Check equality of wiring diagram under permutation of boxes.

When the boxes in the first diagram d1 are permuted according to σ, does it become identical to the second diagram d2?

Get all wires coming out of the port.

Get all wires coming out of the box.

A wiring diagram with a single box connected to its outer ports.

Substitute wiring diagrams for boxes.

Performs one or more substitutions. When performing multiple substitutions, the substitutions are simultaneous.

This operation implements the operadic composition of wiring diagrams (ocompose).

Check compatibility of source and target ports.

The default implementation is a no-op.

Get all wires coming into or out of the box.

Data structure for connecting one layer to another by wires.

This module defines a generic data structure to represent a wiring between one layer of input ports and another layer of output ports. A wiring layer forms a bipartite graph with independent edge sets the input ports and the output ports.

Wiring layers are an auxillary data structure. They are not very interesting in their own right, but they can be a useful intermediate representation. For example, a morphism expression comprising generators, compositions, products, and wiring layers is intermediate between a pure GAT expression (which has no wiring layers, but may have identities, braidings, copies, etc.) and a wiring diagram, which is purely graphical.

Number of input or output ports in a layer.

Object in the category of wiring layers.

Connection by wires of one layer to another.

Morphism in the category of wiring layers.

Completely connected wiring layer.

The layer's underlying graph is the complete bipartite graph.

Convert a wiring layer into a wiring diagram.

Wiring layer representing the wires between two boxes in a wiring diagram.

Wiring diagrams as a symmetric monoidal category and as an operad.

This module provides a high-level functional and algebraic interface to wiring diagrams, building on the low-level imperative interface. It also defines data types and functions to represent diagonals, codiagonals, duals, caps, cups, daggers, and other structures in wiring diagrams.

Box wrapping another box.

Represents unary operations on boxes in wiring diagrams.

Junction node in a wiring diagram.

Junction nodes are used to explicitly represent copies, merges, deletions, creations, caps, and cups.

Port value wrapping another value.

Represents unary operations on ports in wiring diagrams.

A list of ports.

The objects in categories of wiring diagrams.

Apply functor in a category of wiring diagrams.

Defined by compatible mappings of ports and boxes.

Add junction nodes to wiring diagram.

Transforms from the implicit to the explicit representation of diagonals and codiagonals. This operation is inverse to rem_junctions.

Implicit copy in wiring diagram.

Copies are represented by multiple outgoing wires from a single port and deletions by no outgoing wires.

Implicit merge in wiring diagram.

Merges are represented by multiple incoming wires into a single port and creations by no incoming wires.

Wiring diagram of nested caps made out of junction nodes.

Wiring diagram of nested cups made out of junction nodes.

Wiring diagram with a junction node for each of the given ports.

Explicit copy in wiring diagram.

Copies and deletions are represented by junctions (boxes of type Junction).

Explicit merge in wiring diagram.

Merges and creations are represented by junctions (boxes of type Junction).

Merge adjacent junction nodes into single junctions.

Operadic composition of wiring diagrams.

This generic function has two different signatures, corresponding to the two standard definitions of an operad (Yau, 2018, Operads of Wiring Diagrams, Definitions 2.3 and 2.10).

This operation is a simple wrapper around substitution (substitute).

Remove junction nodes from wiring diagram.

Transforms from the explicit to the implicit representation of diagonals and codiagonals. This operation is inverse to add_junctions.

Algorithms operating on wiring diagrams.

Crossing minimization by sorting a univariate statistic.

The boxes in sources and/or targets are fixed and the boxes in vs are permuted. A permutation σ of the latter is returned, such that vs[σ] are the sorted box IDs. Both one-sided and two-sided crossing minimization are supported, depending on whether just one, or both, of sources and targets are given.

In this simple but popular heuristic algorithm, the boxes are permuted by sorting a univariate statistic of the positions of incoming and/or outgoing wires. Typical choices are:

• mean: the sample mean, yielding the "barycenter method"
• median: the sample median

In both cases, this algorithm has the property that if there is a permutation with no crossings, it will find it.

Put a wiring diagram for a cartesian category into normal form.

This function puts a wiring diagram representing a morphism in a free cartesian category into normal form. Copies and deletions are simplified as much as possible.

Normalize copies in a wiring diagram.

This function maximizes sharing of intermediate computations in a wiring diagram where copies are natural.

This algorithm is basically the same as the congruence closure algorithm on term graphs, in the special case of the empty relation R = ∅ (Baader & Nipkow, 1998, Term Rewriting and All That, Sec. 4.4). The main difference is the possibility of zero or many function outputs.

Normalize deletions in a wiring diagram.

This function removes all unused intermediate computations in a wiring diagram where deletion is natural.

Topological sort of boxes in wiring diagram.

Returns a list of box IDs, excluding the outer box's input and output IDs.

Conventions for serialization of wiring diagrams.

Defines a consistent set of names for boxes, ports, and wires to be used when serializing wiring diagrams, as well as conventions for serializing box, port, and wire attributes.

Serialize abstract wiring diagrams as GraphML.

Serialization of box, port, and wire values can be overloaded by data type (see convert_to_graphml_data and convert_from_graphml_data).

GraphML is the closest thing to a de jure and de facto standard in the space of graph data formats, supported by a variety of graph applications and libraries. We depart mildly from the GraphML spec by allowing JSON data attributes for GraphML nodes, ports, and edges.

References:

• GraphML Primer: http://graphml.graphdrawing.org/primer/graphml-primer.html
• GraphML DTD: http://graphml.graphdrawing.org/specification/dtd.html

Generate GraphML representing a wiring diagram.

Parse a wiring diagram from a GraphML string or XML document.

Read a wiring diagram from a GraphML file.

Write a wiring diagram to a file as GraphML.

Serialize abstract wiring diagrams as JSON.

JSON data formats are convenient when programming for the web. Unfortunately, no standard for JSON graph formats has gained any kind of widespread adoption. We adopt a format compatible with that used by the KEILER project and its successor ELK (Eclipse Layout Kernel). This format is roughly feature compatible with GraphML, supporting nested graphs and ports. It also supports layout information like node position and size.

References:

• KEILER's JSON graph format: https://rtsys.informatik.uni-kiel.de/confluence/display/KIELER/JSON+Graph+Format
• ELK's JSON graph format: https://www.eclipse.org/elk/documentation/tooldevelopers/graphdatastructure/jsonformat.html

Generate a JSON dict representing a wiring diagram.

Parse a wiring diagram from a JSON string or dict.

Read a wiring diagram from a JSON file.

Write a wiring diagram to a file as JSON.